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X28HC256
Read Cycle
t RC
ADDRESS
t CE
CE
t OE
OE
V IH
WE
t LZ
t OLZ
t OH
t HZ
t OHZ
DATA I/O
HIGH Z
DATA VALID
DATA VALID
t AA
NOTES:
4. t LZ min., t HZ , t OLZ min. and t OHZ are periodically sampled and not 100% tested, t HZ and t OHZ are measured with C L = 5pF, from the point when
CE, OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
5. For faster 256k products, refer to X28VC256 product line.
Write Cycle Limits
TYP
Write Cycle Time
PARAMETER
SYMBOL
t WC (Note 7)
MIN
(Note 6)
3
MAX
5
UNIT
ms
Address Setup Time
Address Hold Time
Write Setup Time
Write Hold Time
CE Pulse Width
OE HIGH Setup Time
OE HIGH Hold Time
WE Pulse Width
WE HIGH Recovery (page write only)
Data Valid
Data Setup
Data Hold
Delay to Next Write After Polling is True
t AS
t AH
t CS
t CH
t CW
t OES
t OEH
t WP
t WPH (Note 8)
t DV
t DS
t DH
t DW (Note 8)
0
50
0
0
50
0
0
50
50
50
0
10
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
μs
Byte Load Cycle
t BLC
0.15
100
μs
NOTES:
6. Typical values are for T A = +25°C and nominal supply voltage.
7. t WC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device
requires to automatically complete the internal write operation.
8. t WPH and t DW are periodically sampled and not 100% tested.
11
FN8108.3
September 21, 2011
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